1. Technical Field
The present invention relates to a processor chip. In particular, the present invention relates to specifying multiple voltage domains of a signal and macros in a processor chip using a set of design attributes. Still more particular, the present invention relates to specifying multiple voltage domains of signals and macros in a processor chip using a set of design attributes and validating the logical interconnections and physical implementations of the signal and macros based on the set of design attributes.
2. Description of Related Art
Logic and circuit designers use hardware design tools, such as VHDL or other high-level design language, to design circuit connections and hardware components to be included in a processor chip. However, as processor chips become increasingly complex, more and more units or functions are incorporated into a single piece of silicon, for example, system on a chip. The increase of units or functions leads to difficulty in managing power domains, since each individual unit may require a different power domain. A power domain comprises a number of components that shared the same voltage level. Each power domain may be powered on or off at different times.
In addition, there may be thousands of macros, each comprises a collection of interconnecting transistors, on a given processor chip. Thus, it is very difficult to determine which power domain a macro should be on and ensure that all voltage crossings have the proper conversion circuitry. Furthermore, if one power domain is turned off, protection has to be implemented on other domains.
On the other hand, it is also difficult with the existing design tools for designers to validate the physical implementation of a processor chip with the logical design. For a processor chip, physical implementation is the process of specifying the transistors and the interconnections of those transistors that implement the logical behavior described in the high level design language. Existing design tools fail to provide an adequate solution for validating the voltage connections in the physical implementation, because the connections can only be validated manually. Thus, a designer has to know exactly what power supply all of the components and circuits must use in order to validate the design. In other words, designers have to manually specify each macro's power pin to the correct power grid and manually inspect each voltage connection on the macros to verify correctness.
In addition, there is no synchronization between voltage supply levels defined in the logical design and the physical implementation, since existing design tools fail to carry voltage supply level specified in the logical design to the physical implementation. Thus, mistakes will only be found once the design is implemented in actual hardware. Problems with voltage domains or voltage conversions between macros can result in a non-operational chip or a chip whose operation is significantly limited. Therefore, it would be advantageous to have an improved method that allows designer to specify different power domains of signals and macros in a processor chip, and synchronizes the logical design with physical implementation, such that correctness of the design may be automatically validated in the physical implementation to ensure that logical design is correctly implemented.